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G8MNY > TECH 01.09.26 16:04l 87 Lines 3661 Bytes #8 (0) @ WW
BID : 3868_GB7CIP
Read: GUEST
Subj: Darlington & Quasi Darlington
Path: JH4XSY<F1OYP<EA7HQL<ED1ZAC<CX2SA<VE3CGR<K1AJD<GB7BED<EI2GYB<GB7CIP
Sent: 260901/0652Z @:GB7CIP.#32.GBR.EURO #:3868 [Caterham Surrey GBR] $:3868_GB
From: G8MNY@GB7CIP.#32.GBR.EURO
To : TECH@WW
By G8MNY (Updated May 06)
(8 Bit ASCII graphics use code page 437 or 850, Terminal Font)
This simple way to improve the current gain of a transistor just use 2 in
cascade, often used in PSUs & AF output stages and even the odd RF signal amp.
Two separate devices can be used or in a single package.
NORMAL Collector
DARLINGTON レトトトトエ /|\
T1 ウ/ ウ |
Base トトトトトエ ウ 1V Current
/|\ ウ\e ウ/ Saturated Gain HFE = T1 x T2
| タトトエ T2 |
1-1.5V ウ\e |
タ - - -> ウ \|/
Emitter
This method has the 2 transistors of the same type, and has the disadvantage of
higher bias voltage.
QUASI ウ Collector!
DARLINGTON ウ/e /|\
NPN レトトエ T2 |
T1 ウ/ ウ\ PNP 1V
Base トトトトトトエ ウ Saturated Gain HFE = T1 x T2
/|\ ウ\e ウ |
0.6V タトトトトエ \|/
タ - - -> ウ Emitter
This is often used where T1 is a PNP & T2 is a cheaper high power NPN.
To speed up the 2nd transistor turn off, a low R is often used base to emitter
in either configuration.
AS USED IN A PUSH PULL AMP
DARLINGTON 3A
Quasi レトトトトツトトRbsトトトツトトトトトトトトツトトトトトトトトトトトトトトo-oトトトトトトツトトトト<+70V
Complementary ウ Rc ウ/ T3 ウ Fuse ウ From Bridge
Class B Output ウ テトトトトトトエ NPN ウ +ウ Rectifier
=== ウ 6mA ウ\e ウ/ T5 ===
Cbsウ _ウ_ テトトトトトトエ NPN Cpowerウ e.g. 50V @ 2A
ウ \_/ D1 ウ .2Aウ\e ウ transformer
ウ ウBias 100R ウ ウ
ウ ウ ウ Re 4A Pk ウ
レトトツチトトトト)トトトトトトトトチトトトトトトトトナトトトトトトトツトトトトトソ ウ
Rnfb ウ _ウ_ D2 Re ウu1 ウ+ ウ
ウ+ ウ \_/ レトトトトトトトトエ === === Cls ウ
=== ウ ウ ウ/e T2 ウ ウ ウ ウ
Cnfbウ Rb テトトトトトトエ PNP ウ ウ レチソ/ウLS ウ
ウ ウ ウ/ ウ\ ウ/ T4 8R タツル\ウ8R ウ
AF>トトRinトエテトチトトチトトトエNPN テトトトトトトエ NPN 1W ウ 50W RMS ウ
Input Cin T1 ウ\e 100R ウ\e ウ ウ ウ
トトトトトトトトトトトトトトトトトトチトトトトトトトトチトトトトトトトトチトトトトトトトチトトトトトチトトトトトトトトトチトトトト<0v
CLASS A STAGE QUASI COMPLIMENT ZOBAL LOAD
COMPONENT VALUES
Input Z = Rin, e.g. 10K
XCin = Rin @ 10Hz, e.g. 2uF
Rb sets 35V on output, ((Rc+Rs) x T1Hfe), e.g. 330K
Gain = (Rnfb//Rb)/Rin, e.g. 10x = 150K
XCnfb = Rnfb @ < 10Hz, e.g. 1uF
T1= 100mA 100V 100x 1W NPN device
T2 & T3 = 1A 100V 30x 5W, e.g. TIP30 PNP & TIP29 NPN
T4 & T5 = 15A 100V 20x 115W on heatsink, e.g. 2N3055
100R in T4 & 5 base-emitter, ensure they turn off properly.
D1 & D2 drop the 1.3V needed to just under bias outputs, e.g. 1N4148
Re maintain thermal stability, e.g. 0R22 2W
Rc sets the peak +ve output current (e.g.1/2 x LS x T5Hfe x T3Hfe) e.g. 2K2 2W
Cbs & Rbs make a bootstrap to maintain current through Rc.
Rbs = Rc/2 e.g. 1K 1W
XCbs = Rbs @ < 10Hz e.g. 30uF @ 50V
XCls = LS @ < 10Hz e.g. 1000uF @ 50V
XCpower = LS @ < 20Hz, assuming 100Hz supply from bridge, e.g. 4700uF @ 80V
Zobal network keeps the output terminated at HF when the LS is open circuit,
for stability.
In practice there would be more gain stages in front providing 3V RMS drive and
more N.F.B. for lower overall distortion, but this circuit should work OK.
Why don't U send an interesting bul?
73 De John, G8MNY @ GB7CIP
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